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STA304A
DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDXTM
PRODUCT PREVIEW
s s
s s s s s s s
STA304AEND TO END DIGITAL AUDIO INTEGRATED SOLUTION * DSP Functions: - DIGITAL VOLUME CONTROL - SOFT MUTE - BASS and TREBLE - PARAMETRIC EQ PER CHANNEL - BASS MANAGEMENT FOR SUBWOOFER - AUTO MUTE ON ZERO INPUT DETECTION 4+1 DIRECT DIGITAL AMPLIFICATION (DDXTM) OUTPUT CHANNELs 6 CHANNELs PROGRAMMABLE SERIAL OUTPUT INTERFACE (by default I2S) 4 CHANNELs PROGRAMMABLE SERIAL INPUT INTERFACE (by default I2S) STEREO S/PDIF INPUT INTERFACE Intel AC'97 LINK (rev. 2.1) INPUT INTERFACE FOR AUDIO AND CONTROL ON CHIP AUTOMATIC INPUT SAMPLING FREQUENCY DETECTION 100 dB SNR SAMPLE RATE CONVERTER (1KHz SINUSOIDAL INPUT) I2C CONTROL BUS LOW POWER 3.3V CMOS TECHNOLOGY
TQFP44 ORDERING NUMBER: STA304A
s s
s
EMBEDDED PLL FOR INTERNAL CLOCK GENERATION (1024x48 kHz = 49.152 MHz) 6.144 MHz EXTERNAL INPUT CLOCK OR BUILT-IN INDUSTRY STANDARD XTAL OSCILLATOR VARIABLE DIGITAL GAIN UP TO 24dB (0.75dB STEP)
1.0 DESCRIPTION The STA304A Digital Audio Processor is a single chip device implementing end to end digital solution for audio application. In conjunction with STA500 power bridge it gives the full digital DSP-to-power high quality chain with no need for audio Digital-toAnalog converters between DSP and power stage.
s s
BLOCK DIAGRAM
SA 11 SCL 10 SDA 9
LRCKI / SYNC BICKI / BIT_CL
3 4
29
LEFT_A LEFT_B RIGHT_A RIGHT_B SLEFT_A SLEFT_B SRIGHT_A SRIGHT_B LFE_A LFE_B
I2C I2S ROM DDX
30 27 28 33 34 23
SDI_1 / SDATA_OUT 1 SDI_2 / SDATA_IN 2
RXP RXN
24 18 19
S/PDIF SRC DSP
21 22
43 43
LRCKO BICKO
I2S
43 SDO_1 SDO_2 SDO_3
RAM AC97
43 43
RESET
7
PLL
PowerDown
35
EAPD
14 XTI
15 XTO
43 CKOUT
44 PWDN
March 2002
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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STA304A
1.0 DESCRIPTION (continued) The device supports two main configurations as far as input sources: AC'97 input or IIS/SPDIF input: selection is made via a dedicated pin (AC97_MODE pin). The AC97 can be configured to work in two different ways: 'Full Compliant' mode and 'Proprietary' mode which enables more features. The selection of the operating mode is done via a specific bit in a Vendor Reserved register (see bit 0: AC97_FC_mode in the CRA register, address 5Ah). The 'Full Compliant' mode is compliant with rev. 2.1 of AC97 link specifications. This link can provide up to 6 input audio channels with sampling frequency of 44.1, 48, 88.2, 96 kHz, and the related controls. In the IIS/SPDIF mode, a stereo S/PDIF and a 4 channels three-wires programmable serial input interface work in mutually exclusive way. Two channels with sampling frequency in the continuous range from 32 to 96 kHz are supported by the S/PDIF interface. Up to four channels with sampling frequency varying continuously from 32kHz up to 96 kHz are supported by the programmable serial interfaces. Among the different configurations, also the standard IIS protocol is supported. An embedded high quality sample rate converter (SRC) resamples input data at the internal fixed sampling frequency of 48 kHz for DSP operations. The DSP is a 20x20 bit core audio processor performing several user controlled parametric algorithms, among them are dynamic and static equalization, Bass, Treble, Volume control and more. The DSP operates at 49.152MHz (1024xfs). This frequency is generated by an internal PLL with programmable multiplication factor (x2 or x8). This device has 5 channels Direct Digital Amplification (DDXTM technology), performing high efficiency class-D PWM output signals used to drive directly external power bridge stages (STA500). In addition a 6 channel digital output programmable interface (supporting IIS standard protocol) is embedded for applications with commercial audio D/A converters. The output sampling frequency is fixed at 48 kHz when the interface operates as master. In addition an oversampled clock (256xfs or 512xfs) is provided externally for the D/A converters. An IIC interface allows full programmability of internal algorithms and control registers via an external controller. An arbitration logic handles access conflicts to embedded control registers (which may occur as a consequence of contemporary access to control registers by AClink, IIC and DSP blocks). Figure 1. DSP data processing
SL/SR/LFE BASS REDIR CNT L/R
L,R,SL,SR,LFE,CNT
STATIC & DINAMIC EQ L/R
L,R,SL,SR,LFE VOLUME
I2S + DDX
CENTER VOLUME
PHANTOM CENTER
L/R
BASS TREBLE
CNT
I2S
D01AU1310
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STA304A
PIN CONNECTION (Top view)
SLEFT_A
34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
CKOUT
LRCKO
36
GND_5
SDO_3
SDO_2
SDO_1
VDD_5
PWDN
SCKO
44
43
42
41
40
39
38
37
EAPD
35
SDI_1/SDATA_OUT SDI_2/SDATA_IN LRCKI/SYNC BICKI/BIT_CLK VDD_1 GND_1 RESET AC97_MODE SDA SCL SA
1 2 3 4 5 6 7 8 9 10 11
SLEFT_B VDD_4 GND_4 LEFT_A LEFT_B RIGHT_A RIGHT_B VDD_3 GND_3 SRIGHT_A SRIGHT_B
TEST_MODE
VDD_2
XTI
XTO
GND_2
VCC
RXP
RXN
VSS
LFE_B
LFE_A
D00AU1160
PIN FUNCTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME SDI_1 / SDATA_OUT SDI_2 / SDATA_IN LRCKI / SYNC BICKI / BIT_CLK VDD_1 GND_1 RESET AC97_MODE SDA SCL SA TEST_MODE VDD_2 XTI XTO GND_2 I O I I I I/O I TYPE I I/O I/O I/O DESCRIPTION Input I2S Serial Data 1 / AC97 Output Data Input I2S Serial Data 2 / AC97 Input Data Input I2S Left/Right Clock / AC97 Synch. Clock Input I2S Serial Clock / AC97 Bit Clock Digital Supply Voltage Digital Ground Global Reset (This pin is sensed only after 2 clock cycles) AC97 Enable / Disable (1=AC97; 0=I2S/ SPDIF) I2C Serial Data I2C Serial Clock Select Address (I2C / AC97) Test Mode (Active High) Digital Supply Voltage Crystal Input (Clock input) Crystal Output Digital Ground Analog IN CMOS Out Oscill. Pad CMOS Schmitt In Pull-Up CMOS Schmitt In Pull-Down CMOS In / CMOS Out 2mA CMOS In CMOS In CMOS PAD TYPE CMOS Schmitt In CMOS In / CMOS Out 2mA CMOS In / CMOS Out 2mA CMOS In / CMOS Out 4mA
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STA304A
PIN FUNCTION (continued)
PIN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NAME VCC RXP RXN VSS LFE_B LFE_A SRIGHT_B SRIGHT_A GND_3 VDD_3 RIGHT_B RIGHT_A LEFT_B LEFT_A GND_4 VDD_4 SLEFT_B SLEFT_A EAPD LRCKO SDO_1 SDO_2 SDO_3 SCKO GND_5 VDD_5 CKOUT PWDN O I O O O I/O O O O I/O O O O O O O O O I I TYPE DESCRIPTION Analog Supply Voltage S/PDIF receiver positive S/PDIF receiver negative Analog Ground Pwm LFE (subwoofer) output channel (B) Pwm LFE (subwoofer) output channel (A) Pwm Surround Right output channel (B) Pwm Surround Right output channel (A) Digital Ground Digital Supply Voltage Pwm Right output channel (B) Pwm Right output channel (A) Pwm Left output channel (B) Pwm Left output channel (A) Digital Ground Digital Supply Voltage Pwm Surround Left output channel (B) Pwm Surround Left output channel (A) External Amplifier Powerdown (Active Low) Output I2S Left/Right Clock Output I2S Serial Data 1 Output I2S Serial Data 2 Output I2S Serial Data 3 Output I2S Serial Clock Digital Ground Digital Supply Voltage Clock Output (12 /24 MHz) Device Powerdown (Active Low) CMOS Out 8mA CMOS In Pull-Up CMOS Out 3mA CMOS Out 3mA CMOS Out 2mA CMOS In / CMOS Out 2mA CMOS Out 2mA CMOS Out 2mA CMOS Out 2mA CMOS In / CMOS Out 4mA CMOS Out 3mA CMOS Out 3mA CMOS Out 3mA CMOS Out 3mA CMOS Out 3mA CMOS Out 3mA CMOS Out 3mA CMOS Out 3mA Analog In Analog In PAD TYPE
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD Vi Vo Tstg Top PDD PDA Power Supply Voltage on input pins Voltage on output pins Storage Temperature Operative ambient temperature Power Consumption Digital Power Consumption Analog Parameter Value -0.3 to 4 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -40 to +150 -20 to +85 tbd tbd Unit V V V C C mW mW
THERMAL DATA
Symbol Rthj-amb Parameter Thermal resistance Junction to Ambient Value 85 Unit C/W
ELECTRICAL CHARACTERISTCS (VDD = 3.3V 0.3V; Tamb = 0 to 70 C; unless otherwise specified) DC OPERATING CONDITIONS
Symbol VDD Tj Power Supply Voltage Operating Junction Temperature Parameter Value 3.0 to 3.6V -20 to 125 C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol Iil Iih Vesd Parameter Low Level Input Current Without pull-up device High Level Input Current Without pull-up device Electrostatic Protection Test Condition Vi = 0V Vi = VDD = 3.6V Leakage < 1A Min. -10 -10 2000 Typ. Max. 10 10 Unit A A V Note 1 1 2
Note 1: The leakage currents are generally very small, < 1na. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model
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STA304A
DC ELECTRICAL CHARACTERISTICS
Symbol Vil Vih Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = X mA 0.85*VDD 0.8*VDD 0.4*VDD Test Condition Min. Typ. Max. 0.2*VDD Unit V V V V 1,2 1,2 Note
Note 1: Takes into account 200mV voltage drop in both supply lines Note 2: X is the source/sinc current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Ipu Rpu TR TCK
Pull-up current
Vi = 0V; VDD = 3.3V
-25
-66
-125
A K ns ns
1
Equivalent Pull-up resistance Reset Active Time Master Clock Period
50 2*TCK 1 ----------------49.152
Note 1: Min condition: Vdd = 3.0V, 125C Min process; Max. condition: Vdd = 3.6 V, -20C max process.
DIGITAL CHARACTERISTICS-SPDIF RECEIVER (RXP,RXN pins only, SPDIF - MODE = ANALOG) ZIN VTH VHY Input Resistance Dufferential Input Voltage Input Hysteresis 200 50 k mV mV
2.0 AC'97 BANK REGISTER OVERVIEW The AC 97 interface is compliant to `Audio Codec 97 - Revision 2.1' specification, as far as the protocol used. All the registers described in this specification, including Standard, Vendor Reserved and Extended Audio (AC 97 2.0) registers, are available in this device, but just relevant registers which are described in paragraph 11 (Register Summary) are implemented. The ATE mode feature has been implemented for test purpose: for related details refer to the `Audio Codec 97 - Revision 2.1' specification. 2.1 Reading AC 97 Registers Since the AC97 register bank has been implemented as a contiguous RAM space (from a DSP point of view) the content of the RAM itself will be returned as the result of a read operation. This should be followed as a general rule of thumb but, where not possible, a different approach has been used. Hereby is a list of the registers, and bits, that do not follow this rule or that have a particular handling:
*
CodecID_0, CodecID_1: These two bit are respectively bits 14 and 15 of registers 28h (Extended Audio ID) and 3Ch (EWxtended Modem ID). When a read operation of these registers is performed the returned value is based on the status of the SA pin: CodecID_0 report the status of SA pin, CodecID_1 always report 0. Other bits of these registers return the related RAM register contents. Also note that the status of the SA pin is not readable by the DSP. PR4: The bit 12 of register 26h (Powerdown, ctrl/start) is used to set the AC97 BIT_CLK and SDATA_IN signal to a low state. In response to a Warmers the status of this bit is set back to its default 0 value. In response
*
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STA304A
to a read request the actual value of this signal is returned, not the RAM content. Due to this fact the relative RAM register content can be incongruous.
*
Regs. 2Ch, 2Eh and 30h (Audio Sample Rate Control): These three registers are used to setup the sample rate when the Variable Rate Mode is enabled. In response to a read request on one of these registers the actual value returned can be either BB80h or AC44h, depending on the status of an internal hardware signal; the status of this signal is updated every time a write operation into one of these register is performed. For more details regarding a specific bit please refer to the appropriate paragraph.
In order to be as much compliant to the specification as possible two different mode of operation has been introduced. Using the AC97_FC_Mode configuration bit the interface can be configured in Full-Compliant mode (default): in this mode the value returned as response to a read operation will be properly masked in order to set `reserved' bits to 0, as from specification. This operation is performed on all registers included the Standard or Extended Audio address space. If the Full-Compliant mode is not selected the full 16 bits data from the corresponding RAM register will be returned with no further manipulation. If an odd-addressed register reading operation is performed the following scheme is adopted: * * * Slot 0: Slot 2 (data): report valid bit set to 1 for both slot 1 and slot 2 report all 0s
Slot 1 (address): report the odd address
2.2 Writing AC 97 Registers When a write operation into one of the available AC97 registers is performed the entire 16 bits data word is written into the related RAM register (also reserved bits are passed through). Some bits of some register may have a corresponding hardware register (Flip-Flop), used to control the internal status of the device: in this case the value of the FF is also updated every time a write to the related RAM register is performed. The status of these FF is reverted to their default values after a hardware reset or a software reset (writing to reg. 00h) request has been issued; as a consequence also the DSP will have to reset the RAM register contents. Some register may have a different behaviour from the one depicted above. Here is a brief summary of those registers.
* * *
Regs. 7Ch and 7Eh: These are the Vendor ID1 and ID2 registers. Any write request to one of these will be ignored. Regs. 28h: The `Extended Audio ID Register' is read only. Therefore any write request will be ignored. Regs. 26h: When a write request is issued the actual data written into the RAM register is `xxxxxxxxxxxx1110', where `x' stands for the incoming data. Regs. 2Ah: When a write request is issued the actual data written into the RAM register is `xxxxxx0111xxxxxx', where `x' stands for the incoming data. Regs. 32h and 34h: Any write request into one of these ADC sample rate register will result in the value BB80h written into the corresponding RAM register.
*
*
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STA304A
3.0 I2S INPUT INTERFACE CONFIGURATION In order to configure the I2S input interface the Configuration Register B (CRB) can be used. Using the 3 I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them.
MODE 0 1 2 3 4 5 6 7 # of SLOTS 32 32 32 32 24 Not valid 24 24 W. LENGHT 24 24 16 24 24 Not valid 16 24 ALIGNMENT Left Left Right Right Left Not valid Right Right DELAY SLOT No Yes No No No Not valid No No Slave only Reserved, do not use. MSb first only. Slave only Slave only MSb first only NOTES
By default standard I2S input interface slave is provided (mode 1 in bits 0,1,2 of register CRB, I2S_BICK_Pol = 1 and I2SI_LRCK_Pol = 0 with some register) 3.1 Switching characteristics (10 pf load; Fsm=32 KHz to 96KHz):
BICKI frequency (master mode): (slave mode): BICKI pulse width low (T0) (slave mode): BICKI pulse width high (T1) (slave mode): BICKI active to LRCKI edge delay (T2): BICKI active to LRCKI edge setup (T3): SDI valid to BICKI active setup (T4): BICKI active to SDI hold time (T5): BICKI falling to LRCKI edge (T6) (master mode): 3.072MHz Max 6.4 MHz min 40 ns. min 40 ns. min 20 ns. min 20 ns. min 20 ns. min 20 ns. min 3 ns; max 9 ns.
Figure 2.
T2 T3
LRCKI T1 T6 BICKI T4 SDI
D00AU1244
T0
T5
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STA304A
4.0 I2S OUTPUT INTERFACE CONFIGURATION In order to configure the I2S output interface the Configuration Register B (CRB) can be used. Using the 3 I2SO_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them.
MODE 0 1 2 3 4 5 6 7 # of SLOTS 32 32 32 32 24 Not valid 24 24 W. LENGHT 24 24 16 24 24 Not valid 16 24 ALIGNMENT Left Left Right Right Left Not valid Right Right DELAY SLOT No Yes No No No Not valid No No Slave only Reserved, do not use. MSb first only. Slave only Slave only MSb first only NOTES
By default standard I2S output interface master is provided (mode 1 in bits 8,9,10 of register CRB, I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register) 4.1 Switching characteristics (10 pf load; Fsm=48 KHz):
SCKO frequency (master mode): (slave mode): SCKO pulse width low (T0) (slave mode): SCKO pulse width high (T1) (slave mode): SCKO active to LRCKO edge delay (T2): SCKO active to LRCKO edge setup (T3): SDO valid to SCKO active setup (T4): SCKO active to SDO hold time (T5): SCKO falling to LRCKO edge (T6) (master mode): SCKO falling to SDO edge(T7) (master mode): (slave mode): 64 Fsm 64 Fsm min 40 ns. min 40 ns. min 20 ns. min 20 ns. min 20 ns. min 20 ns. min 2 ns; max 8 ns. min 2 ns; max 8 ns. min 6 ns; max 17 ns
Figure 3.
T2 T3
LRCKO T1 T6 BICKO T4 SDO
D00AU1245
T0
T7
T5
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STA304A
5.0 SAMPLE RATE CONVERTER The sample rate converter resamples the selected input data source in order to send to the DSP an audio stream with a fixed frequency of 48 KHz. The following picture show the basic architecture. Figure 4.
Interpolation FIR x2
DATA_IN Fs
2 x Fs
Interpolation FIR x2 Anti-Alias FILT
Fs
4xFs or 2xFs
Sinc 6 Async.
DATA_OUT 48KHz
Thresh. Selector
LRCK_IN
DRLL
RATIO
The selection between X2 Fir interpolation or direct antialiasing Filter on input data is made automatically by the threshold selector block. If the input sampling frequency (measured by DRLL) is high than the SRC threshold (see Table 2 section 12.9), the direct antialising filter is selected, otherwise if the input frequency is lower than the SRC threshold, the X2 FIR filter is added the data path. A 1kHz hysteresis is fixed around the SRC threshold nominal values of tab. 2 section 12.9, to prevent unstable oscillations. In figure 5 the DRLL lock phase is shown for 32kHz,44.1kHz, 48kHz and 96kHz input frequency. Note that only after this phase (including the flat part of the graph) the SRC performances are in spec. Figure 5. DRLL lock delay
x 10
4
10
9
8
Esimated Frequency
7
6
5
4
3
2
1
0
0
0.05
0.1 Second
0.15
0.2
0.25
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STA304A
6.0 DAP INPUT STAGE The device provides 3 mutually exclusive input interfaces: I2S, S/PDIF and AC97. Hereby is a small description of the characteristics for each of them and a table showing how to select it. Figure 6.
I2C
I2S_SPDIF_Sel
I2S
LRCK SRC_Bypass
S/PDIF SRC
DDX
YRAM LEFT RIGHT SL/CENTER SR CENTER LFE
DSP
AC97
AC97_Sel
YRAM LEFT RIGHT SL/CENTER SR CENTER LFE
PLL_Factor PLL_Bypass
PLL
MCK
I2S
/1024 /2 or /8
XTI
LRCK
CK_OUT
6.1 Input from I2S Using this input interface a maximum of 4 channels can be sent to the DSP. As detailed in the related paragraph this I/F can be configured both as master or slave. When in master the sampling frequency is fixed to 48 KHz and the SRC can be bypassed using the SRC_Bypass configuration bit (in CRA register). If slave operation is selected the full range between 32KHz and 96KHz is supported but the SRC must always be in the processing path (no bypass). In order to select this interface the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel bit must be 0. 6.2 Input from S/PDIF This interface is compliant with the AES/EBU IEC 958, S/PDIF and EIAJ CP-340/1201 professional and consumer standards. The full range from 32 KHz up to 96 KHz is supported but the SRC bypass option must be switched off. Using the SPDIF_Mode bit this interface can be configured as digital or analog input. If the analog mode is selected the line receiver can decode differential as well as single ended inputs. The receiver consists of a differential input Schmitt Trigger comparator with 50 mV of hysteresis, which prevents noisy signals from corrupting the data recovered. The minimum input differential voltage is 200 mV. If the digital mode is selected only the single ended operation is supported; the input signal should be CMOS compliant. In order to select this interface the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel must be 1. 6.3 Input from AC97 In order to select this interface the AC97_MODE pin must be tied to VDD (I2S_SPDIF_Sel bit `is don't care). The AC97 interface can be configured either as primary or secondary device using the external configuration pin SA. This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec 97
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STA304A
specification. The following table summarize the slot usage for each one the these frequencies:
Freq. 48 44.1 88.2 * 96 Slot 3 Left Left Left Left Slot 4 Right Right Right Right Center Center Slot 6 Center Slot 7 Surr.L Surr.L Slot 8 Surr.R Surr.R Left (n+1) Left (n+1) Right (n+1) Right (n+1) Center (n+1) Center (n+1) Slot 9 LFE Slot 10 Slot 11 Slot 12
* Slots 3, 4 and 6 are always requested. Slots 10, 11 and 12 are requested only when needed.
The following table summarize the different input possibilities:
Input from I2S (Master) I2S (Slave) S/PDIF AC97 AC97 AC97 AC97 Channels 4 4 2 6 3 4 3 Available Freq. (KHz) 48 32..96 32..96 48 96 44.1 (VRA) 88.2 (VRA) Bypass Yes No No Yes * No No No Left, Right, SL, SR, Center, LFE Left, Right, Center Left, Right, SL, SR Left, Right, Center Notes Bypass is user selectable
* In this configuration the BYPASS is always active, regardless SRC_Bypass bit in reg. 5Ah
7.0 PLL In order to generate the internal 49.152 MHz clock a low-jitter PLL has been included in the device. It can be configured to work either with a multiplication factor of x8 or x2, in order to fit an external frequency reference of 6.144 MHz or, respectively, 24.576 MHz. This could be useful when the device is configured to work in AC97 slave mode where the master clock is 24.576 MHz. To select the multiplication factor the PLL_Factor bit can be used. Using the PLL_Bypass bit the PLL section can be bypassed, allowing direct connection of the internal clock to the XTI pin. When this option is selected an external frequency of 49.152 MHz should be provided to the device. In this condition the PLL is automatically powered-down. 8.0 POWERDOWN MANAGEMENT The powerdown capability and its logic behaviour is shown in Figure 7 - Powerdown management . Basically there are three powerdown requests which comes from the extern of the device and will cause a different powerdown condition: External PWDN pin - this signal will turn-off the device which, as a consequence, will enter the powerdown mode (all the device clocks are stopped). The device will exit this state as soon as the PWDN pin is deasserted. PR5 bit (reg. 26h, bit 13) - Setting this bit will cause a partial powerdown of the device: infact all the clocks will be suspended, except that used to keep the AC97 and I2C cells alive. In this way, using either of these input interfaces, it'll be possible to resume from this state simply resetting the PR5 bit. EAPD bit (reg.26h, bit 15) - The External Amplifier PowerDown bit controls the state of the related pin (EAPD) which, in turn, is used to switch off the external power chip.
-
-
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STA304A
Figure 7. Powerdown management
LR LFE
DSP
SL SR Requests
&
LR LFE SR SL
reg. 02h bit 15 reg. 36h bit 15 reg. 38h bit 07 reg. 38h bit 15
EAPD (reg. 26h, bit 15) &
OR
EAPD pin (ACTIVE Low)
PWDN pin (reg.7EFh, bit0) & (Active Low)
Chip powerdown
PR5 (reg.26h, bit 13)
&
Internal CK disable
In order to avoid any possible pop-noise while switching between the various powerdown modes a particular masking technique has been adopted to drive the actual controlling signals: as shown in the above figure the 3 powerdown requests will inform the DSP using the related bits in specific registers. After that the DSP performs a software fade-out of the channels volume and, finally, activates the MUTE flags of the various channels. The actual controlling lines are the result of a logical AND operation between the relative request signals and the 4 channel MUTE bits (LR, LFE, SL and SR). Moreover the external power chip will be turned off (via the EAPD pin) not only as a consequence of an EAPD request, but also as a consequence of a PR5 or PWDN requests: this solution will prevent any possible noise or glitch.
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STA304A
9.0 BASS MANAGEMENTAND EQ The STA304A has the ability to redirect the sound to the SBW channel and to pass each channel through a 4stage cascaded 2nd order IIR filter. With the combination of the DDX gain/compressor (CRA register bits 2-3) a dynamic EQ can be implemented. Beside that, a special Side-Firing sound can be achieved by enabling this feature available with the ready made filter topology on the surround channels. 9.1 Bass Redirection Figure 8.
L C (*) R LS RS
Scale RS Scale LS Scale R Scale C Scale L
LR Filter Phantom
L
(IIS C)
LR Filter
R LS RS
Sur Filter
Sur Filter
(*)
LFE
Scale LFE
+
SBW Filter
SBW
There is an option to redirect each input channel to the SBW output channel. The Scale factor of each channel should be set with values in the range of 0 (no redirection) to -1 (full redirection). About setting the scaling factors registers, see paragraph 10. The redirection is taking place when the bit 0 of the Bass Management Register (add.72h) is set (see section 12.13). Together with the static EQ option (following section), by setting appropriate filters, a full bass management solution is available.
(*) Note: C and LFE channels are available only with 6 channels AC97 input. In case of 4 channels I2S, only L, R, LS, RS are available
9.2 Static EQ Figure 9.
Input
Scale in Factor
bi-quad0
bi-quad1
bi-quad2
bi-quad3
Output
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STA304A
Each channel has a 4 stage cascaded 2nd order filter. The user can set each filter coefficients (see paragraph 10). The coefficient for the Left and Right channels are common, as well as the coefficients for the surrounds. There is also an input scaling factor for each channel which can be set with values from 0 to -1. The scaling factor should be set to an appropriate value that will prevent the filter going into saturation. The Static EQ filters are activated by setting Static EQ and Side Firing register (add. 70h, see section 12.12). 9.3 Surround Side Firing Instead of the normal filters described in the previous section above, a special topology is available for the surround channels: Figure 10.
Left Surround Input Left Surround Output
Scale in Factor
bi-quad0
bi-quad1
+ +
and Phase Invering bi-quad2 Right Surround Input bi-quad3 Right Surround Output
Scale in Factor
bi-quad0
bi-quad1
bi-quad2
bi-quad3
By designing appropriate filters special surround sound can be achieved for a system which its surround speakers are located next to the front speakers and are rotated to the sides (see picture). The Side firing topology is enabled by setting Static EQ and Side Firing register (add. 70h, see section 12.12). Figure 11. Speaker System with Side-Firing positioning
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10.0 COEFFICIENT HANDLING In order to implement the Static EQ filters and the Bass management, a RAM space for user coefficients has been included in this device: starting from address 240h (YRAM) there are 69 x 20 bit registers available for this purpose. In order to be able to read or write into these registers an indirected addressing approach must be followed by the application software. As showed in Figure 8 there are two AC'97 dedicated registers (4 x 8 bits registers from I2C point of view) to access the coefficient table. In register 78h (78h + 79h in I2C addressing) the 16 low bits of the coefficient are stored (by the user in case of a write operation, by the logic in case of a read operation); the higher 4 bits are stored in the lowest nibble of register 7Ah (7Bh in I2C addressing). The address of the coefficient on which the R/W operation must be performed is stored in the high byte of register 7Ah. The address is made adding the coefficient index to the base location 40h. To select between Read or Write operation the 'R' bit in register 7Ah (7Bh in I2C addressing) must be properly setup. The actual read/write operation will start after the register 7Ah (7Bh in I2C addressing) has be written. The following paragraphs will explain this in more details. Figure 12. Coefficient registers usage
AC97 I2C
Bit 15 Coefficient[15..0] Coeff. Address (8 bits)
Bit 0
78h 7Ah
78h 7Ah
79h 7Bh
R-x-x-x Coefficient[19..16]
R : set this bit to 1 for reading a coefficient, 0 for writing it.
10.1 Reading a coefficient value Depending on the bus used to read the coefficient the following steps must be followed: * Reading from AC'97 - write 8 bit INDEX 40h and R/W bit at AC97 address 7Ah - read 16 lower data bits at AC97 address 78h - read 4 higher data bits at AC97 address 7Ah Reading from I2C - write 8 bit address at I2C address 7Ah coeff INDEX + 40h - write R/W bit at I2C address 7Bh - read 8 middle data bits at I2C address 78h - read 8 lower data bits at I2C address 79h - read 4 higher data bits at I2C address 7Bh
*
10.2 Writing a coefficient value Depending on the bus used to write the coefficient the following steps must be followed: * Writing from AC'97 - write 16 lower bit data at AC97 address 78h - write 8 bit INDEX + 40h and R/W bit and 4 higher data bits at AC97 address 7Ah Writing from I2C - write 8 middle data bits at I2C address 78h - write 8 lower data bits at I2C address 79h - write 8 bit address at I2C address 7Ah coeff INDEX + 40h - write 4 higher data bits and R/W bit at I2C address 7Bh
*
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10.3 Coefficient map
Index (decimal) 0 1 ... 4 5 ... 19 20 ... 39 40 41 42 43 44 45 ... 59 60 61 62 63 64 65 66 67 68 index (hex) 0h 1h ... 4h 5h ... 13h 14h ... 27h 28h 29h 2Ah 2bh 2Ch 2dh ... 3bh 3Ch 3dh 3Eh 3Fh 40h 41h 42h 43h 44h 6 SBW redirection factors 3 scale in factors 20 SBW filter coef. 20 Surrounds filter coef. 20 LR filter coef. coefficient LR00 (b2) LR01 (b0-1) ... LR04 (b1/2) LR10 (b2) ... LR34 (b1/2) SUR00 ... SUR34 SBW00 (b2) SBW01 (b0-1) SBW02 (a2) SBW03 (a1/2) SBW04 (b1/2) SBW10 ... SBW34 -scale_in LR -scale_in SUR -scale_in SBW -scale_LSBW -scale_RSBW -scale_LSSBW -scale_RSSBW -scale_CSBW -scale_LFESBW default value 00000h 00000h ... 00000h 00000h ... 00000h 00000h ... 00000h 00032h 80032h 7C7EAh 81C6Fh 00032h 00000h ... 00000h 80000h 80000h 80000h C0000h C0000h C0000h C0000h C0000h 80000h
Filter coefficients: CHx0 = b2 CHx1 = (b0)-1 CHx2 = a2 CHx3 = (a1)/2 CHx4 = (b1)/2
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where CH stands for LR,SUR or SBW and x stands for the filter number (0..3). The filter equation is Yn = Xn+((b0)-1)*Xn + 2*((b1)/2)*Xn-1 + b2*Xn-2 - 2*((a1)/2)*Yn-1 - a2*Yn-2 = = b0*Xn + b1*Xn-1 + b2*Xn-2 - a1*Yn-1 - a2*Yn-2 The coefficient registers are 20 bits wide and should be in the range [-1..1) (80000h to 7ffffh). Scaling factor registers: For the filters Xn = - (-scale_in) * CHn , where CHn is the value before scaling and Xn is the input to the filter. For the SBW redirection SBWn = -S (-scale_CH)*CHn The scaling factor registers are 20 bits wide and should be in the range [-1..0] (80000h to 00000h). SBW redirection: -1 for maximum redirection and 0 for no redirection. Filter scaling: -1 for maximum input and 0 for no input to filter. 11.0 I2C BUS SPECIFICATION The STA304A supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master always starts the transfer and provides the serial clock for synchronisation. The STA304A is always a slave device in all its communications. 16bit registers are addressed as two 8 bit registers. The high byte has even address, while the low byte has odd address. For example, reading from register 02 (16bit) means read registers 02 (HIGH BYTE) and 03 (LOW BYTE) from I2C. 11.1 COMMUNICATION PROTOCOL 11.1.1Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high are used to identify START or STOP condition. 11.1.2Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state.A START condition must precede any command for data transfer. 11.1.3Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA304A and the bus master. 11.1.4Acknowledge bit An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. 11.1.5Data input During the data input the STA304A samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low. 11.2 DEVICE ADDRESSING To start communication between the master and the STA304A, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address
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and read or write mode. The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition. In STA304A the I2C interface has two device address depending on SA pin configuration 0011110 when SA = 0, and 0011111 when SA = 1. The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA304A identifies on the bus the device address and, if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte is the internal space address. 11.3 WRITE OPERATION Following a START condition the master sends a device select code with the RW bit set to 0. The STA304A acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA304A again responds with an acknowledge. 11.3.1Byte write In the byte write mode the master sends one data byte, this is acknowledged by STA304A. The master then terminates the transfer by generating a STOP condition. 11.3.2Multibyte write The multibyte write mode can start from any internal address. The transfer is terminated by the master generating a STOP condition. Figure 13. Write Mode Sequence
ACK BYTE WRITE START DEV-ADDR SUB-ADDR ACK DATA IN ACK
RW
STOP
ACK MULTIBYTE WRITE START DEV-ADDR SUB-ADDR
ACK DATA IN
ACK DATA IN
ACK
RW
D98AU825B
STOP
Figure 14. Read Mode Sequence
ACK CURRENT ADDRESS READ START NO ACK
DEV-ADDR
DATA
RW ACK ACK SUB-ADDR
STOP ACK DEV-ADDR DATA NO ACK
RANDOM ADDRESS READ START
DEV-ADDR
RW RW= ACK HIGH DEV-ADDR DATA
START ACK DATA
RW ACK DATA NO ACK
STOP
SEQUENTIAL CURRENT READ START
STOP ACK ACK SUB-ADDR DEV-ADDR ACK DATA ACK DATA ACK DATA NO ACK
SEQUENTIAL RANDOM READ START
DEV-ADDR
RW
START
RW
D98AU826A
STOP
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12.0 REGISTER SUMMARY 12.1 Reset Register (add. 00h)
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0
Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns 00E4h as it is the ID code of the part and its 3D Stereo Enhancement type (See AC'97 revision 2.1 specification, section 6.3.1). 12.2 LR Volume Register (add. 02h)
D15 Mute D14 ML6 D13 ML5 D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 X D6 MR6 D5 MR5 D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0
This register manage the stereo (both right and left channels) output signal volumes. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. ML6 through ML0 is for the left channel level, MR6 through MR0 is for the right channel. There are two options: in 'Full Compliance' operating mode (bit 0 in the CRA register, address 5Ah, is set to '0') only 6 bits are active (Mx0 to Mx5) and each step corresponds to 1.5 dB. In 'Proprietary' mode (bit 0 in the CRA register is set to '1') Mx0 to Mx6 can have the values between 0h to 68h (110 1000) and each step corresponds to 1dB. Greater values are undefined. The default value is 8000h (1000 0000 0000 0000), which corresponds to 0 dB attenuation with mute on.
Mute 0 0 0 1 Mx6...Mx0 x00 0000 x01 1111 x11 1111 xxx xxxx Function 0 dB Attenuation 46.5dB Attenuation 94.5dB Attenuation dB Attenuation
'Full Compliance' Mode
Mute 0 0 0 Mx6...Mx0 000 0000 001 1111 011 1111 ... 0 0 0 0 0 0 0 0 1 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 xxx xxxx Function 0 dB Attenuation 31dB Attenuation 63dB Attenuation ... 97dB Attenuation 99dB Attenuation 100dB Attenuation 102dB Attenuation 104dB Attenuation 107dB Attenuation 111dB Attenuation dB Attenuation dB Attenuation
'Proprietary' Mode
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12.3 Tone Control Register (add. 08h)
D15 X D14 X D13 X D12 X D11 BA3 D10 BA2 D9 BA1 D8 BA0 D7 X D6 X D5 X D4 X D3 TR3 D2 TR2 D1 TR1 D0 TR0
This register support tone controls (bass and treble). The step size is 2dB. Writing a 0000h corresponds to +12dB of gain. Center frequencies (from which gains are measured) are 160Hz for Bass and 5,000Hz for Treble. The default value is 0F0Fh, which corresponds to bypass of bass or treble gain. The tone feature is implemented only on the L and R front channel.
TR3... TR0 or BA3... BA0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 +12 dB of gain +10 dB of gain +8 dB of gain +6 dB of gain +4 dB of gain +2 dB of gain +1 dB of gain 0 dB of gain -1 dB of gain -2 dB of gain -4 dB of gain -6 dB of gain -8 dB of gain -10 dB of gain -12 dB of gain Bypass Function
12.4 Powerdown Ctrl/Staus Register (PCSR) : add. 26h
D15 EAPD D14 D13 PR5 D12 PR4 D11 D10 D9 D8 D7 D6 D5 D4 D3 1 D2 1 D1 1 D0 0
BIT 12
R/W R/W
RST 0
NAME PR4
DESCRIPTION Setting this bit to 1 the BIT_CLK and the SDATA_IN signal will be fixed to the digital low level. To resume the normal operation either an hardware reset or a softReset must be performed. In order to set the device in a powerdown-like condition this bit must be set to 1. This will stop the device internal clock: only the PLL and AC97, I2C clocks will still be running. DSP should start power-down sequence in order to accomplish this request. The value of this bit should be checked by the DSP in order to recognize an external power amplifier power-down request. As a consequence the DSP should start the power-down sequence (volume fade-out)
13
R/W
0
PR5
15
R/W
1
EAPD
NOTE: Bits D0..D3 will be masked to the showed value before writing into the RAM registers, other bits will simply pass through.
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12.5 Extended Audio ID Register (add. 28h)
D15 0 D14 ID0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 1 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1
The Extended Audio ID is a read only register that identifies which extended audio features are supported (See AC'97 revision 2.1 specification, section A.2.1). The extended features supported are Variable Rate PCM Audio (VRA), Double- Rate PCM Audio (DRA), PCM Center (CDAC), PCM Surround (SDAC) and PCM LFE (LDAC). Codec_ID0 report the status of SA pin. Codec_ID1 always report 0. Hence, the configurations are primary (00) if SA pin is 0 or Secondary (01) if SA pin is 1. 12.6 Extended Audio Status and Control Register (add. 2Ah)
D15 D14 D13 D12 D11 D10 D9 0 D8 1 D7 1 D6 1 D5 D4 D3 D2 D1 DRA D0 VRA
* VRA= 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ signaling) * DRA= 1 enables Double- Rate Audio mode Bits D9- D6 are read only status of the extended audio feature readiness. When a write request is issued the actual data written into the RAM register is 'xxxxxx0111xxxxxx'. For more details refer to AC'97 rev 2.1, section A.2.2 12.7 Audio Sample Rate Control Registers (add. 2Ch - 34h) D15
SR15
D14
D13
D12
D11
D10
D9
SR9
D8
SR8
D7
SR7
D6
SR6
D5
SR5
D4
SR4
D3
SR3
D2
SR2
D1
SR1
D0
SR0
SR14 SR13 SR12 SR11 SR10
In VRA mode, two frequencies are supported 48000(BB80h) Hz and 44100(AC44h) Hz. If one of these value written to the 2Ch register, that value will be echoed back when read, otherwise the closest (higher in case of a tie) sample rate supported is returned. The content of 2Eh and 30h registers is copied from the 2Ch register. If the Double Rate Audio (DRA) mode is active, the sample rate programmed will be multiplied by 2x. For example: When running at 88.2 kHz, the DRA bit will be programmed to 1, and the sample rate programmed would be 44.100. The default value after cold or warm register reset for these registers (BB80h) is 48 kHz. The content of the ADC sample rate registers (32h and 34h) stays always BB80h. 12.8 6-Channel Volume Control Register (add. 36h - 38h)
D15 Mute Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CNT0 RSR0
LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Mute CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 LSR6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 Mute RSR6 RSR5 RSR4 RSR3 RSR2 RSR1
These read/write registers control the output volume of the optional four PCM channels, and values written to the fields behave the same as the Play Master Volume Register (Index 02h), which offers attenuation but no gain. There is an independent mute (1= on) for each channel. The default value after reset for this registers (8080h) corresponds to 0 dB attenuation with mute on.
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12.9 Configuration Register A (CRA) : add. 5Ah
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SRC_By DRLL_d SRC_TH SRC_TH SPDIF_ I2S_SP MCKOU PLL_By PLL_Fac DDX_P DDX_ZD DDX_Rst DDX_Ga DDX_Ga I2SI_DBU AC97_F pass bg R_1 R_0 Mode DIF_Sel T_Mode pass tor wrMode _Enable in_1 in_0 FF_Mode C_Mode
BIT 0
R/W R/W
RST 0
NAME AC97_FC_Mode
DESCRIPTION AC'97 Full Compliant Mode (0 to enable). When in FC mode any read of registers will return only valid bits: bits marked as `reserved' by AC'97 v2.0 specification will return 0, regardless of the RAM contents. Enable DoubleBuffer mode for the I2S input interface (write1 to enable this option) . This is strongly required if this interface is operated in slave mode at 48KHz, synchronous with the input source. In this condition also Sample Rate Converter Bypass is suggested to omprove performances DDX Gain setting (LSb/MSb). These two bits, concatenated, will set the DDX stage gain and the compression as shown in Table 1. (These setting is active only if bit 15 reg 62h is 0) DDX Reset (active high) DDX Zero Detect feature. If this bit is 1 the feature is enabled. DDX Power Mode (TRUTH Table). Using this bit it is possible to select the truth table used by the DDX digital output stage (1 = ST standard) PLL Factor (x2 or x8). It should be used according to the input frequency provided to the device: 1 (x8) when 6.144 MHz are provided, 0 (x2) when 24.576 MHz. PLL Bypass. Setting this bit to 0 will bypass the PLL; internal master clock will be directly connected to XTI pin. MckOut mode: 12.288 MHz (1) or 24.576 MHz (0). I2S - S/PDIF Selector. Select the input source: set to 0 for I2S input, 1 for S/PDIF input. S/PDIF Mode. Set to 0 to select Analog mode, 1 to select Digital mode. Sample Rate threshold (LSb/MSb). These bits are used to select the threshold frequency enabling the SRC anti-alias filter. Table 2 shows the threshold selections. DRLL Debug Mode. When this mode is activated (1) the DRLL digital ratio is latched on the output channels instead of the audio data. SRC Bypass. Setting this bit to 1 the SRC block can be bypassed and the selected input I/F is directly connected to the DSP.
1
R/W
0
I2SI_DBUFF_Mode
2 3 4 5 6 7
R/W R/W R/W R/W R/W R/W
0 0 1 1 1 0
DDX_Gain_0 DDX_Gain_1 DDX_Rst DDX_ZD_Enable DDX_PwrMode PLL_Factor
8 9 10 11 12 13 14 15
R/W R/W R/W R/W R/W R/W R/W R/W
1 0 0 0 1 0 0 0
PLL_Bypass MCKOUT_Mode I2S_SPDIF_Sel SPDIF_Mode SRC_THR_0 SRC_THR_1 DRLL_dbg SRC_Bypass
NOTE: In TEST_MODE -> PLL_Bypass = 0.
Table 1. SRC Threshold
SRC_THR_0 0 0 1 1 SRC_THR_1 0 1 0 1 Threshold Frequency INACTIVE 58.875 to 61.125kHz 78.973 to 81.000kHz always active
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Table 2. DDX gain
DDX_GAIN_0 0 0 1 1 DDX_GAIN_1 0 1 0 1 DDXGain 1x 2x 2x 3x DDX Compression NO NO YES YES
DDX Gain Compression Since a full-scale output of the GC/Vol block is mapped to full output modulation, any signal exceeding 0 dBFS at the output of the GC/Vol block will be clipped. The purpose of the compression algorithm is to reduce the gain of the system when 0 dBFS has been exceeded such that clipping does not take place, thus performing an output limiting function. This would yield a constant Vout once the gained input exceeds 0 dBFS. With DDX_GAIN_0 = 1, the output of the GC/Vol block is compared to a threshold set just below 0 dBFS. When the output of GC/Vol exceeds this threshold the gain of system is reduced following a set time-constant and gain-reduction rate. This reduction in gain is stored as a variable. If subsequently the output of GC/Vol remains below a separate lower threshold for a set amount of time the gain is then increased following another timeconstant and gain rate. Thus, seven different constants determine the attack, release, and limiting characteristics of the compression algorithm. These constants have been tuned to sound as musical as possible when the dynamic range of a recording is being reduced due to 0 dBFS being exceeded. Figure 15. Compression response to 500 Hz sine at 0 dBFS with gain of +10 dB
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12.10Configuration Register B (CRB) : add. 5Ch
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2SO_M I2SO_LR I2SO_LR I2SO_BC I2SO_BI I2SO_Ali I2SO_Ali I2SO_Ali I2SI_MS I2SI_LR I2SI_LR I2SI_BC I2SI_BIC I2SI_Alig I2SI_Alig I2SI_Alig SbLSb CK_Master CK_Pol K_Master CK_Pol gn_2 gn_1 gn_0 bLSb CK_Master CK_Pol K_Master K_Pol n_2 n_1 n_0
BIT 0 1 2 3
R/W R/W R/W R/W R/W
RST 1 0 0 1
NAME I2SI_Align_0 I2SI_Align_1 I2SI_Align_2 I2SI_BICK_Pol
DESCRIPTION I2S (Input) Alignement. Using these bits the word alignement can be adjusted with respect to the LRCK edges. Please refer to the related paragraph for more details. The default value is mode 1. I2S (Input) BICK Polarity. This bit should be configured according to the used serial protocol. In order to sample incoming data on the rising edge (data changes on the falling edge) this bit should be set to 1. Set to 0 to reverse the sampling edge. I2S (Input) Master/Slave Selection. The I2S input interface can be configured as both master or slave: if the master mode is selected (1) the BICK line will be an output (64 x 48KHz fixed). Otherwise (0) slave mode is selected and this line is an input. I2S (Input) LRCK Polarity. Set to 0 to receive LEFT samples when LRCK is low, 1 otherwise. I2S (Input) Master/Slave Selection. The I2S input interface can be configured as both master or slave: if the master mode is selected (1) the LRCK line will be an output (48KHz fixed). Otherwise (0) slave mode is selected and this line is an input (continuous frequency between 32KHz and 96KHz). I2S (Input) MSb/LSb Selection. Use this bit to select how the sample word is received by the I2S input interface: set to 0 to configure as LSb first, 1 MSb first. I2S (Output) Alignemt. Using these bits the word alignement can be adjusted with respect to the LRCK edges. Please refer to the related paragraph for more details. The default value is mode 1. I2S (Output) BICK Polarity. This bit should be configured according to the used serial protocol. In order to sample outcoming data on the rising edge (data changes on the falling edge) this bit should be set to 1. Set to 0 to reverse the sampling edge. I2S (Output) Master/Slave Selection. The I2S output interface can be configured as both master or slave: if the master mode is selected (1) the BICK line will be an output (64 x 48KHz fixed). Otherwise (0) slave mode is selected and this line is an input. I2S (Output) LRCK Polarity. Set to 0 to transmit LEFT samples when LRCK is low, 1 otherwise. I2S (Output) Master/Slave Selection. The I2S output interface can be configured as both master or slave: if the master mode is selected (1) the LRCK line will be an output. Otherwise (0) slave mode is selected and this line is an input. In any case the frequency is fixed at 48 kHz I2S (Output) ) MSb/LSb Selection. Use this bit to select how the sample word is transmitted by the I2S output interface: set to 0 to configure as LSb first, 1 MSb first.
4
R/W
0
I2SI_BCK_Master
5 6
R/W R/W
0 0
I2SI_LRCK_Pol I2SI_LRCK_Master
7 8 9 10 11
R/W R/W R/W R/W R/W
1 1 0 0 1
I2SI_MSbLSb I2SO_Align_0 I2SO_Align_1 I2SO_Align_2 I2SO_BICK_Pol
12
R/W
1
I2SO_BCK_Master
13 14
R/W R/W
0 1
I2SO_LRCK_Pol I2SO_LRCK_Master
15
R/W
1
I2SO_MSbLSb
NOTE: Power-on default values will configure serial input interface as I2S Slave and the output interface as I2S Master.
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12.11Phantom Center Register (add. 60h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Phantom
Setting bit 0 enables the phantom center channel feature. When this feature is on, the content of the center channel is split and added to the L and R channels. 12.12DDX Gain Register (add. 62h)
D15 bypass D14 GCEN D13 Vol4 D12 Vol3 D11 Vol2 D10 Vol1 D9 Vol0 D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
bypass: GCEN: Vol4...Vol0
0
means that the DDX gain depends from CRA bits 2 and 3
1 the DDX gain depends from D13-D9 bits plus D14 bit (CRA bit 2 and 3 are ignored) if D15 = 1 set (1) or remove (0) the ddx output compressor
Vol 00000 00001 00010 ---01111 10000 ---11101 11110 11111 +1.50 +0.75 0 +12 +11.25 dB +23.25 +22.5 +21.75
The STA304A provides continuous digital gain and limiting functionality. Digital gain is variable from 0dB to +23.25dB in 0.75dB steps based in the 62h register when the bit 15 is set. If the bit 15 is not set, th STA304A defaults to the original Gain/Limiting truth table based on DDX_Gain bits (12.9). The GCEN bit when set enables limiting to prevent clipping. This limiter uses a peak detect algoritthm for attack and a RMS detect for release. The attack threshold is set at full DDX output power and will therefore reduce the gain when clipping is occuring. The release threshold is set slightly below this to allow for a minimum dynamic range. Figure 16.
LIMITER
RMS
GAIN/VOLUME
INPUT
GAIN
ATTENUATION
SATURATION
OUTPUT
D01AU1313
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12.13Static EQ and Side Firing Register (add. 70h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 EQ1 D0 EQ0
This register controls the activation of the Static EQ and the Side Firing surround sound.
EQ1 0 0 1 EQ0 0 1 x EQ off (default) EQ enabled Side Firing + EQ
For more information on setting EQ parameters, see Paragraph 9 .2
12.14Bass Management Register (add. 72h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bass Mng
Setting bit 0 activate the Bass Management. For more information on Bass Management, see Paragraph 9 .1. Default is 0h.
12.15Bypass Register (add. 74h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bypass
Setting bit 0 bypass the DSP block. All channels are bypassed and output equal to input, regardless of all other algorithm register settings (Volume, Tone, Phantom, EQ). Default is 0h
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12.16BIST and Status Register (BASR) : add. 76h
D15 D14 D13 D12 D11
X
D10
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DSP_BIS DSP_BIS DSP_BIS DSP_RA T_Start T_Running T_Stop M
SRC_SP SRC_SP DDX_DP DDX_SP DDX_SP DDX_SP BIST_St BIST_St SPDIF_ SRC_St RAM_2 RAM_1 RAM RAM_3 RAM_2 RAM_1 op art Status atus
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I/F R R W R R R R R R R R/W R/W R R R W
DSP
RST 1 1
NAME SRC_Status SPDIF_Status BIST_Start BIST_Stop DDX_SPRAM_1 DDX_SPRAM_2 DDX_SPRAM_3 DDX_DPRAM SRC_SPRAM_1 SRC_SPRAM_2 AC3_AMEN CH1_AMEN DSP_RAM DSP_BIST_Stop DSP_BIST_Running DSP_BIST_Start
DESCRIPTION When 0, the digital pll in the SRC is LOCKED. When 1 the digital PLL is OUT of LOCK. When 1, the SPDIF interface is out of lock. When 0 the interface is locked to the SPDIF stream input. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enable automuting if AC3 frame header found Enable automuting if no CH1_STATUS bit found Reserved Reserved Reserved Reserved
R
0 0 0 0 0 0 0 0 1 0
R R R R
0 0 0 0
12.17Coefficients Handling Registers (add. 78h - 7Ah)
D15 C15 AD7 D14 C14 AD6 D13 C13 AD5 D12 C12 AD4 D11 C11 AD3 D10 C10 AD2 D9 C9 AD1 D8 C8 AD0 D7 C7 R/W D6 C6 D5 C5 D4 C4 D3 C3 C19 D2 C2 C18 D1 C1 C17 D0 C0 C16
See paragraph 10. 12.18Vendor ID Registers (add. 7Ch - 7Eh) D15 0 0 D14 1 1 D13 0 0 D12 0 0 D11 0 1 D10 0 0 D9 0 1 D8 1 0 D7 0 D6 1 D5 0 D4 0 D3 1 D2 1 REV2 D1 0 REV1 D0 0 REV0
REV7 REV6 REV5 REV4 REV3
These registers are specific vendor identification for the STA304A. The Microsoft's Plug and Play Vendor ID code is "ALJ". The REV7.. 0 field is for the Vendor Revision number. These are read only registers, any write request to one of these will be ignored.
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STA304A
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.37 1.45 0.45 0.20 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 0.002 0.053 0.012 0.004 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.014 0.057 0.018 0.008 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B
C
e
L
K
TQFP4410
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STA304A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved
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(R)
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